1. Field of the Invention
The present invention relates to a logic device in which a signal changing with an external load is output within a prescribed range of a through rate such as a rise time or a fall time while suppressing an unnecessary radiation noise.
2. Description of Related Art
A prescribed range is generally standardized for a through rate (for example, a rise time or a fall time) of an output signal of which a level changes with an external load. For example, standards of a Universal Serial Bus (USB) used for computer peripheral apparatuses have been approved. A signal output from a device transmits through the USB at a data rate of 1.5 M bits per second in a low speed data communication. The USB standards relate to a level of the signal output from the device, and the USB standards require that the output signal is accurately raised up and fallen down within a time-period range of from 75 to 300 nanosecond in the low speed data communication on condition that an external load ranges from 200 pF to 600 pF. Therefore, the through rate of the output signal is required to be fixed within a prescribed range.
As a conventional logic device in which a signal is output within a through rate range regulated in the USB standards, an output buffer circuit disclosed in the Published Unexamined Japanese Patent Application No. 17516 of 1999 (H11-17516) has been known. FIG. 9 is a circuit diagram showing the configuration of the output buffer circuit disclosed in the Patent Application No. 17516 of 1999, and FIG. 10 is a waveform diagram showing simulation results of level changes of output signals in a low speed operation of the output buffer circuit.
As shown in FIG. 9, reference numerals 11, 12, 13, 14, 15, 16, 17 and 18 indicate inverter circuits. Each inverter circuit fundamentally outputs an signal of a high electric level (H level) corresponding to a logical value xe2x80x9c1xe2x80x9d (positive logic) when a p-channel metal oxide semiconductor (MOS) transistor of the inverter circuit is turned on by receiving a signal of a low electric level (L level) corresponding to a logical value xe2x80x9c0xe2x80x9d at a gate of the p-channel MOS transistor. Also, each inverter circuit fundamentally outputs an signal of an L level when an n-channel MOS transistor of the inverter circuit is turned on by receiving a signal of an H level at a gate of the n-channel MOS transistor. The Output of each of the inverter circuits 13, 14, 15 and 16 is controlled according to enable signals LSB and LS or enable signals FSB and FS. Also, by using a source voltage VDD and a reference voltage VSS (VSS is equal to the ground voltage of 0 V), a threshold voltage (that is, a switching voltage) of each of the inverter circuits 11, 13 and 14 is a value higher than (VDDxe2x88x92VSS)/2, and a threshold voltage of each of the inverter circuits 12, 15 and 16 is a value lower than (VDDxe2x88x92VSS)/2. A reference numeral 130 indicates a control circuit, each of reference numerals 140a and 140b indicates a delay circuit, a reference numeral 151 indicates a first-stage buffer, a reference numeral 152 indicates a second-stage buffer, a reference numeral 153 indicates a third-stage buffer, a reference symbol P0 indicates a p-channel MOS transistor of the first buffer 151, and a reference symbol NO indicates an n-channel MOS transistor of the first buffer 151. A reference symbol P1 indicates a p-channel MOS transistor of the second buffer 152, and a reference symbol N1 indicates an n-channel MOS transistor of the second buffer 152. A reference symbol P2 indicates a p-channel MOS transistor of the third buffer 153, and a reference symbol N2 indicates an n-channel MOS transistor of the third buffer 153. A reference symbol Cap indicates a condenser arranged between a node DD and the ground of the voltage VSS.
An operation of the output buffer circuit is described on condition that the logical value of an input signal D is changed from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d in a low mode speed operation according to the positive logic. Also, in this low mode operation, the inverter circuits 13 and 15 are controlled by the enable signals LSB and LS to be operable.
When the logical value of an input signal D is changed from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, a level of a signal output from the inverter circuit 17 is heightened as the level of the input signal D becomes lowered, and the signal is input to the inverter circuit 18. As the level of the signal input to the inverter circuit 18 is heightened, a p-channel MOS transistor PU of the inverter circuit 18 starts to turn off, and an n-channel MOS transistor ND of the inverter circuit 18 starts to turn on. As a result, a charge of the node DD set to the level VDD is discharged to the ground through the n-channel MOS transistor ND. In this case, because the condenser Cap is arranged between the node DD and the ground, as shown in FIG. 10, the level of the node DD is gradually changed from the H level (VDD level) to the L level (VSS level).
Because a threshold voltage Vth11 of the inverter circuit 11 is higher than (VDDxe2x88x92VSS)2, that is, VDD2 in case of VSS=0 V (ground level), as the level of the input signal D is lowered, the level of the input signal D reaches the threshold voltage Vth11 of the inverter circuit 11, and the logical value of a signal Pu1 output from the inverter circuit 11 is changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d before the level of the input signal D reaches VDD/2.
In contrast, the level of the node DD is gradually lowered while being delayed as compared with the lowering of the level of the input signal D, and the level of the node DD reaches a threshold voltage Vth13 of the inverter circuit 13. As a result, as shown in FIG. 10, the level of a signal Pu2 output from the inverter circuit 13 is heightened. That is, the logical value of the signal Pu2 is changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d. In this case, the level change of the signal Pu1 is earlier than that of the signal Pu2. Thereafter, the p-channel MOS transistor P0 of the first-stage buffer 151 and the p-channel MOS transistor P1 of the second-stage buffer 152 start to turn off. Also, the p-channel MOS transistor P2 of the third-stage buffer 153 starts to turn off.
Thereafter, when the level of the input signal D continues to be lowered, a p-channel MOS transistor P10 is rapidly turned on so as to assist the p-channel MOS transistor P1 of the second-stage buffer 152 to be turned off, and a p-channel MOS transistor P11 is rapidly turned on so as to assist the p-channel MOS transistor P2 of the third-stage buffer 153 to be turned off. As a result, as shown in FIG. 10, the level of the signal Pu2 is sharply changed toward the high level (VDD) in the first half of the fall time of the input signal D while changing a waveform of the signal Pu2 stepwise, and a level of a signal Q of an output pad Q is sharply lowered in the middle of the fall time of the signal Q.
Thereafter, when the level of the input signal D is lowered to a threshold voltage Vth12 of the inverter circuit 12 lower than VDD/2, the logical value of a signal Pd1 output from the inverter circuit 12 is changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d. Therefore, the n-channel MOS transistor NO of the first-stage buffer 151 starts to turn on. However, at this time, the level of the node DD, which is set by discharging the charge of the node DD to the ground through the inverter circuit 18, is not lowered to a threshold voltage Vth15 of the inverter circuit 15. Therefore, the n-channel MOS transistor N1 of the second buffer 152 and the n-channel MOS transistor N2 of the third buffer 153 are respectively maintained to an xe2x80x9coffxe2x80x9d condition.
Thereafter, when the level of the node DD reaches the threshold voltage Vth15 of the inverter circuit 15, as shown in FIG. 10, the logical value of a signal Pd2 output from the inverter circuit 15 is changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d. Therefore, the n-channel MOS transistor N1 and the n-channel MOS transistor N2 start to turn on. In this case, because the delaying circuit 140b is arranged between the inverter circuit 15 and the n-channel MOS transistor N2, the level change of the n-channel MOS transistor N2 is later than that of the n-channel MOS transistor N1. Therefore, as shown in FIG. 10, the level of the signal Q of the output pad Q is rapidly lowered to the L level (VSS) in the second half of the fall time of the input signal D.
Accordingly, because the first-stage buffer 151, the second-stage buffer 152 and the third-stage buffer 153 are operated one by one in that order while shifting the level changing timing of the MOS transistors, the through rate of the output signal Q can be set within a prescribed range.
However, as shown in FIG. 10, a point QQ, at which the level of the output signal Q is unevenly fallen down in synchronization with the raising-up of the signal Pd2, occurs during the fall time of the input signal D in the low speed mode operation in the output buffer circuit. Also, in the same manner, another point QQ, at which the level of the output signal Q is unevenly raised up in synchronization with the falling-down of the signal Pu2, occurs during the rise time of the input signal D in the low speed mode operation in the output buffer circuit. The uneven falling-down and uneven raising-up of the level at the points QQ occur because the output pad Q is driven while shifting the changing timing of the transistors. Therefore, the output signal includes higher harmonic wave components at the points QQ, so that there is a drawback that the higher harmonic wave components function as an unnecessary radiation noise in the output signal Q.
A main object of the present invention is to provide, with due consideration to the drawback of the conventional logic device, a logic device in which a signal is output within a prescribed range of a through rate of the signal while suppressing the occurrence of an unnecessary radiation noise.
Also, a subordinate object of the present invention is to provide a logic device in which a cross point of waveforms of two differential signals and a ratio of through rates in the differential signals are respectively set within a prescribed range even though the logic device is used as a differential device outputting each differential signal.
Also, another subordinate object of the present invention is to provide a logic device in which a signal is output while setting a ratio of a rise time to a fall time in the signal within a prescribed range even though a driving performance of a transistor arranged in the logic device differs from a desired driving performance.
The main object is achieved by the provision of logic device in which a pair of output-stage transistors complementarily operated with each other are controlled according to an input signal received at an input terminal to output an output signal corresponding to the input signal to an output terminal and to charge or discharge an external load, comprising:
a control circuit for controlling one output-stage transistor, which is to be controlled to a turn-off condition, to be immediately turned off by a transistor of a strong driving performance, and controlling the other output-stage transistor, which is to be controlled to a turn-on condition, to be successively and smoothly turned on by a plurality of transistors respectively having a weak driving performance while controlling the other output-stage transistor by one transistor of the weak driving performance at a turning-on speed, at which a through rate is set within a prescribed range in a beginning period changing to the turn-on condition.
In the above configuration, when the level of the input signal is suddenly changed, the control circuit is operated. In detail, a transistor of the strong driving performance is operated according to the input signal, so that the output-stage transistor, which is to be controlled to a turn-off condition, is turned off. Because the transistor has the strong driving performance, the output-stage transistor is immediately turned off, so that the output-stage transistor has no relation to the production of an output signal.
Also, a transistor of a weak driving performance is operated according to the input signal to turn on the output-stage transistor to be controlled to a turn-on condition, so that the output signal is produced by the output-stage transistor. However, because the transistor has the weak driving performance, the transistor cannot make the output-stage transistor sharply change a level of the output signal in a beginning period, so that a through rate of the output signal cannot be set within a prescribed range. Therefore, another transistor of another weak driving performance is operated according to the input signal, and the output-stage transistor to be controlled to the turn-on condition is sharply turned on under control of the transistor in the beginning period at a turning-on speed, at which the through rate of the output signal is set within the prescribed range, so as to successively and smoothly change a level of the output signal in the entire level change period of the output signal.
Accordingly, because the output-stage transistor to be controlled to the turn-on condition is rapidly turned on in the beginning period in addition that the output-stage transistor to be controlled to the turn-on condition is gradually turned on in a transitional period following the beginning period, the output signal can be produced by the output-stage transistor while setting a through rate of the output signal within the prescribed range.
Also, because the turning-on speed of the second output-stage transistor in the beginning period is set to successively and smoothly change the level of the output signal in the entire level change period of the output signal, the occurrence of higher harmonic waves based on an uneven level change of a signal can be suppressed Therefore, the occurrence of an unnecessary radiation. noise can be suppressed.
Also, even though the logic device is used as a differential device to output a differential signal as the output signal, a cross point of waveforms of two differential signals can be set within a prescribed range, and a ratio of through rates in the differential signals can be set within a prescribed range.
Also, because the output-stage transistor to be controlled to the turn-on condition is operated under control of the transistors, even though a pull-up resistor or a pull-down resistor is used as the external load, the adverse influence of the pull-up resistor or the pull-down resistor on a rise time or a fall time in the output signal can be prevented by the function of the transistors, so that the rise time and the fall time in the output signal can be set to be equal to each other.
It is preferred that the control circuit comprises:
a first transistor, having a middle driving performance, for functioning in the beginning of a period in which the output-stage transistor to be controlled to the turn-on condition is changed to the turn-on condition and controlling the output-stage transistor, which is to be controlled to the turn-on condition, at the turning-on speed, at which the through rate of the output signal at the output terminal is set within the prescribed range; and
a second transistor, having a weak driving performance, for controlling the output-stage transistor, which is to be controlled to the turn-on condition, in a transition period continued until the output-stage transistor is changed to the turn-on condition and reaches a steady condition and making the output-stage transistor, which is to be controlled to the turn-on condition, output the output signal in which a higher harmonic component is reduced.
In the above configuration, because the second transistor has the low driving performance, the second transistor has substantially no relation to the production of the output signal in the beginning period, but the second driving transistor make the output-stage transistor gradually change the level of the output signal in the transition period following the beginning period. In this case, the rapid level change of the output signal in the beginning period is smoothly succeeded to the gradual level change in the transition period, so that the level of the output signal is smoothly changed during the entire level change period.
Accordingly, the occurrence of higher harmonic waves and the occurrence of an unnecessary radiation noise can be reliably suppressed.
It is preferred that the control circuit comprises:
a first driving cell comprising
a first-conductive-type MOS transistor of a strong driving performance, connected with a terminal of a source level, for controlling the output-stage first-conductive-type transistor to be controlled to the turn-off condition, which is arranged between the terminal of the source level and the output terminal, according to the input signal received in the input terminal so as to be immediately controlled to the turn-off condition; and
a second-conductive-type MOS transistor of a weak driving performance, connected with a terminal of a reference level and complementarily operated with the first-conductive-type MOS transistor, for controlling the output-stage first-conductive-type transistor, which is to be controlled to the turn-on condition, so as to be gradually turned on according to the input signal received in the input terminal,
a second driving cell comprising
a second-conductive-type MOS transistor of a strong driving performance, connected with the terminal of the reference level, for controlling the output-stage second-conductive-type transistor to be controlled to the turn-off condition, which is arranged between the terminal of the reference level and the output terminal, according to the input signal received in the input terminal so as to be immediately controlled to the turn-off condition; and
a first-conductive-type MOS transistor of a weak driving performance, connected with the terminal of the source level and complementarily operated with the second-conductive-type MOS transistor, for controlling the output-stage second-conductive-type transistor, which is to be controlled to the turn-on condition, so as to be gradually turned on according to the input signal received in the input terminal, and
a through rate correcting circuit for controlling the output-stage second-conductive-type MOS transistor to be turned on at the turning-on speed, at which the through rate of the output signal output to the output terminal is set within the prescribed range, in the beginning period, in which the output-stage second-conductive-type MOS transistor is controlled by the second driving cell to be gradually turned on, and controlling the output-stage first-conductive-type MOS transistor to be turned on at the turning-on speed, at which the through rate of the output signal output to the output terminal is set within the prescribed range, in the beginning period, in which the output-stage first-conductive-type MOS transistor is controlled by the first driving cell to be gradually turned on.
The output-stage second-conductive-type MOS transistor and the output-stage first-conductive-type MOS transistor to be controlled to the turn-on condition are controlled by the first and second driving cells to reduce the higher harmonic waves of the output signal, so that the occurrence of an unnecessary radiation noise based on the output signal can be suppressed.
Also, because the output-stage second-conductive-type MOS transistor and the output-stage first-conductive-type MOS transistor to be controlled to the turn-on condition are controlled by the through rate correcting circuit to set the through rate of the output signal within the prescribed range, the through rate of the output signal is set within the prescribed range. Also, even though a pull-up resistor or a pull-down resistor is arranged as the external load, a difference between a rise time and a fall time in the output signal is reduced.
Also, even though the logic device is used as a differential device to output a differential signal as the output signal, a cross point of waveforms of two differential signals can be set within a prescribed range, and a ratio of through rates in the differential signals can be set within a prescribed range.
It is preferred that the through rate correcting circuit comprises:
a second-conductive-type MOS transistor of a middle driving performance, arranged between a gate of the output-stage second-conductive-type MOS transistor and the terminal of the source level, for controlling the output-stage second-conductive-type transistor according to an inverted signal of the input signal received at the input terminal to be turned on at the turning-on speed, at which the through rate of the output signal output to the output terminal is set within the prescribed range, in the beginning period in which the output-stage second-conductive-type MOS transistor is controlled by the second driving cell to be gradually turned on; and
a first-conductive-type MOS transistor of a middle driving performance, arranged between a gate of the output-stage first-conductive-type MOS transistor and the terminal of the reference level, for controlling the output-stage first-conductive-type transistor according to the inverted signal of the input signal received at the input terminal to be turned on at the turning-on speed, at which the through rate of the output signal output to the output terminal is set within the prescribed range, in the beginning period in which the output-stage first-conductive-type MOS transistor is controlled by the first driving cell to be gradually turned on.
Therefore, the through rate correcting circuit sets the through rate of the output signal output to the output terminal within the prescribed range. Also, even though a pull-up resistor or a pull-down resistor is arranged as the external load, a difference between a rise time and a fall time in the output signal is reduced.
Also, even though the logic device is used as a differential device to output a differential signal as the output signal, a cross point of waveforms of two differential signals can be set within a prescribed range, and a ratio of through rates in the differential signals can be set within a prescribed range.
It is preferred that the logic device further comprises a manufacturing error correcting circuit for correcting a ratio of a rise time to a fall time in the output signal output to the output terminal to set the ratio within a prescribed range regardless of a driving performance difference between a group of first-conductive-type MOS transistors and a group of second-conductive-type MOS transistors caused by manufacturing errors.
Therefore, even though a driving performance difference between a group of first-conductive-type MOS transistors and a group of second-conductive-type MOS transistors occurs because manufacturing errors occur in the group of first-conductive-type MOS transistors and the group of second-conductive-type MOS transistors, a ratio of a rise time to a fall time in the output signal can be set within a prescribed range.
It is preferred that the manufacturing error correcting circuit comprises:
a manufacturing error correcting second-conductive-type MOS transistor, connected with the output-stage first-conductive-type MOS transistor in parallel to each other and cooperated with the output-stage first-conductive-type MOS transistor; and
a manufacturing error correcting first-conductive-type MOS transistor, connected with the output-stage second-conductive-type MOS transistor in parallel to each other, cooperated with the output-stage second-conductive-type MOS transistor and complementarily operated with the manufacturing error correcting second-conductive-type MOS transistor.
In the above configuration, in cases where the driving performance of the group of first-conductive-type MOS transistors differs from a desired driving performance, the rise time of the output signal is lengthen. Therefore, the rise time is corrected by the manufacturing error correcting second-conductive-type MOS transistor manufactured to have the desired driving performance. In contrast, in cases where the driving performance of the group of second-conductive-type MOS transistors differs from a desired driving performance, the fall time of the output signal is lengthen. Therefore, the fall time is corrected by the manufacturing error correcting first-conductive-type MOS transistor manufactured to have the desired driving performance.
Accordingly, the ratio in the output-stage first-conductive-type MOS transistor can be reliably set within a prescribed range, and the ratio in the output-stage second-conductive-type MOS transistor can be reliably set within a prescribed range.
The main object is also achieved by the provision of a logic device, comprising:
a control circuit having
a pair of first-stage output transistors, which are complementarily operated with each other and are controlled according to an inverted signal which is obtained by inverting an input signal received at an input terminal and has a strong driving performance, for outputting an output signal corresponding to the input signal to an output terminal and charging or discharging an output load; and
a pair of second-stage output transistors, which respectively have a driving performance stronger than that of the first-stage output transistors and are complementarily operated with each other, for performing an operation in parallel to the operation of the first-stage output transistors and correcting a through rate of the output signal output from the first-stage output transistors to the output terminal, wherein one second-stage output transistor, which is to be controlled to a turn-off condition, is controlled according to the input signal and a delayed input signal obtained by delaying the input signal to be immediately turn off by a transistor of a strong driving performance, and the other second-stage output transistor, which is to be controlled to a turn-on condition, is controlled according to the input signal and the delayed input signal to be turned on in a latter period changing to the turn-on condition while successively and smoothly controlling the other second-stage output transistor at first by a transistor of a weak driving performance and controlling the other second-stage output transistor at a turning-on speed at which the through rate is set within a prescribed range.
Therefore, because the second-stage output transistor to be controlled to the turn-on condition is smoothly turned on by the transistor of the weak driving performance at first, the occurrence of higher harmonic waves based on an uneven level change of a signal can be suppressed, and the occurrence of an unnecessary radiation noise can be suppressed. Thereafter, because the second-stage output transistor having a driving performance stronger that that of the first-stage output transistor is turned on to set the through rate within the prescribed range, even though a pull-up resistor or a pull-down resistor is arranged as the external load, a difference between a rise time and a fall time in the output signal can be reduced.
Also, even though the logic device is used as a differential device to output a differential signal as the output signal, a cross point-of waveforms of two differential signals can be set within a prescribed range, and a ratio of through rates in the differential signals can be set within a prescribed range.
It is preferred that the first-stage output transistors are a first-stage output first-conductive-type MOS transistor, which is connected with a terminal of a source voltage, and a first-stage output second-conductive-type MOS transistor, which is connected with a terminal of a reference voltage, complementarily operated with each other, the second-stage output transistors are a second-stage output first-conductive-type MOS transistor, which is connected with the terminal of the source voltage, and a second-stage output second-conductive-type MOS transistor, which is connected with the terminal of the reference voltage, complementarily operated with each other, and the control circuit comprises
a first driving cell comprising:
a first-conductive-type MOS transistor of a strong driving performance for controlling the second-stage output first-conductive-type transistor, which is to be controlled to the turn-off condition, to be immediately turned off according to the delayed input signal; and
a second-conductive-type MOS transistor of a weak driving performance, complementarily operated with the first-conductive-type MOS transistor, for controlling the second-stage output first-conductive-type transistor, which is to be controlled to the turn-on condition, to be successively and smoothly turned on in the latter period changing to the turn-on condition at the turning-on speed at which the through rate is set within the prescribed range, and
a second driving cell comprising:
a second-conductive-type MOS transistor of a strong driving performance for controlling the second-stage output second-conductive-type transistor, which is to be controlled to the turn-off condition, to be immediately turned off according to the delayed input signal; and
a first-conductive-type MOS transistor of a weak driving performance, complementarily operated with the second-conductive-type MOS transistor, for controlling the second-stage output second-conductive-type transistor, which is to be controlled to the turn-on condition, to be successively and smoothly turned on in the latter period changing to the turn-on condition at the turning-on speed at which the through rate is set within the prescribed range.
Therefore, the higher harmonic waves of the output signal can be suppressed by the second-stage output first-conductive-type transistor and the second-stage output second-conductive-type transistor controlled to be turn on by transistors of the weak driving performance arranged in the first and second driving cells, the through rate of the output signal can be set within the prescribed range.
Also, because the driving performance of the second-stage output first-conductive-type transistor and the second-stage output second-conductive-type transistor, which is stronger than that of the first-stage output first-conductive-type transistor and the first-stage output second-conductive-type transistor, is sufficient to influence on the external load. Therefore, even though a pull-up resistor or a pull-down resistor is arranged as the external load, a difference between a rise time and a fall time in the output signal can be reduced.
Also, even though the logic device is used as a differential device to output a differential signal as the output signal, a cross point of waveforms of two differential signals can be set within a prescribed range, and a ratio of through rates in the differential signals can be set within a prescribed range.
It is preferred that the control circuit further comprises:
an AND gate for producing a first driving signal from the input signal and the delayed input signal according to an AND logic and transmitting the first driving signal to a gate of the first-conductive-type MOS transistor of the first driving cell and a gate of the second-conductive-type MOS transistor of the first driving cell, the first driving signal performing a first level change in response to a first level change of the input signal and performing a second level change in response to a second level change of the delayed input signal; and
an OR gate for producing a second driving signal from the input signal and the delayed input signal according to an OR logic and transmitting the second driving signal to a gate of the first-conductive-type MOS transistor of the second driving cell and a gate of the second-conductive-type MOS transistor of the second driving cell, the second driving signal performing the second level change in response to the second level change of the input signal and performing the first level change in response to the first level change of the delayed input signal.
In the above configuration, when the level of the input signal is suddenly lowered to the low level (the first level change), the first driving signal lowered to the low level in response to the input signal is output from the AND gate, and the second driving signal lowered to the low level in response to the delayed input signal is output from the OR gate. In contrast, when the level of the input signal is suddenly heightened to the high level (the second level change), the first driving signal heightened to the high level in response to the delayed input signal is output from the AND gate, and the second driving signal heightened to the high level in response to the input signal is output from the OR gate. Therefore, the second-stage output signal gradually level-changing in the second half period of the level change of the second-stage output signal is output from a second-stage output circuit of the second-stage output transistors.
Accordingly, the output signal can be produced while setting a through rate of the output signal within a prescribed range. Also, the occurrence of higher harmonic waves based on an uneven level change of a signal can be suppressed, and the occurrence of an unnecessary radiation noise can be suppressed.